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[Other] cpu的VERILOG描述

Description: RISC CPU的VerilogHDL描述-RISC CPU Verilog HDL description
Platform: | Size: 369497 | Author: 陈俊 | Hits:

[SourceCode] risc cpu

Description: risc 8 bit cpu core verilog
Platform: | Size: 139464 | Author: maxwellnul | Hits:

[ARM-PowerPC-ColdFire-MIPS] ethernet_verilog

Description: 这是一个很好的Verilog 编写的8位RISC CPU源码（可做为MCU），并且包括完整的C 语言的测试代码。-This is a very good preparation Verilog 8-bit RISC CPU source (available as MCU), and includes a complete C language test code.
Platform: | Size: 78848 | Author: 张念华 | Hits:

[VHDL-FPGA-Verilog] risc_cpu

Description: 这是一个Verilog HDL编写的RISC cpu的程序，该程序共10个子程序，实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。-This is the RISC cpu code which writed by Verilog HDL.This code has ten subprogram which came true the simple RISC cpu. Beginner can reference this example to study the Hardware discription language and the design manner. This program have passed the Modelsim validate.
Platform: | Size: 44032 | Author: 施向东 | Hits:

[VHDL-FPGA-Verilog] RISC8.ZIP

Description: 简单的一个8位RISC，Verilog HDL代码,类型为pic16c57-a simple eight RISC, Verilog HDL code, the type of pic16c57
Platform: | Size: 80896 | Author: 陈正一 | Hits:

[VHDL-FPGA-Verilog] 16_risc_cpu

Description: 一个支持精简指令的16位的risc cpu，可综合-a directive to support the streamlining of the 16 RISC CPU can be integrated
Platform: | Size: 163840 | Author: 董 | Hits:

[Software Engineering] risc8

Description: 经典计算机体系结构RISC8的源代码（Verilog），包括CPU、内存、寄存器等的实现-classic computer architecture RISC8 the source code (Verilog), including CPU, memory, such as the realization Register
Platform: | Size: 82944 | Author: snake | Hits:

[VHDL-FPGA-Verilog] risc_spm

Description: advanced digital design with the verilog hdl-advanced digital design with the verilog h dl
Platform: | Size: 4096 | Author: zhenglao | Hits:

[VHDL-FPGA-Verilog] RiscCpu

Description: 用verilog编写的risc mcu -verilog prepared with the risc mcu
Platform: | Size: 9216 | Author: 谢迪 | Hits:

[VHDL-FPGA-Verilog] riscmcu

Description: 精简CPU设计，需要的可以下来看看,是VERILOG语言写的-streamlined CPU design, the need to be down look at the language is written in verilog
Platform: | Size: 79872 | Author: 磊 | Hits:

[VHDL-FPGA-Verilog] VCDwtHDLV

Description: < 大型RISC处理器设计--用描述语言Verilog设计VLSI芯片>>光盘-<Large RISC processor design- Verilog design language used to describe VLSI chip>> CD-ROM
Platform: | Size: 874496 | Author: wiyn | Hits:

[ARM-PowerPC-ColdFire-MIPS] compu1

Description: 用verilogHDL写的一个risc处理器-VerilogHDL write with a RISC processor
Platform: | Size: 625664 | Author: frank | Hits:

[ARM-PowerPC-ColdFire-MIPS] RISC_Core.ZIP

Description: 这是一篇关于8位RISC CPU设计的文章，其中包含了用Verilog语言编写的CPU内核程序-This is an 8-bit RISC CPU on the design of the article, which includes using the Verilog language CPU core procedures
Platform: | Size: 340992 | Author: jinzhoulang | Hits:

[Other Embeded program] RISC8

Description: 已经测试过的RISC8的verilog源码和说明还包括编译环境和测试程序等-Has been tested RISC8 and description of Verilog source code also includes the compiler, such as the environment and testing procedures
Platform: | Size: 400384 | Author: 缪德芳 | Hits:

[OS Develop] minirisc.tar

Description: verilog code .descrip the risc cpu.download from opencores.org-verilog code. descrip the risc cpu.download from opencores.org
Platform: | Size: 74752 | Author: 刘科麟 | Hits:

[VHDL-FPGA-Verilog] alu

Description: 16位RISC CPU的ALU，使用VHDL编写-16-bit RISC CPU
Platform: | Size: 2048 | Author: 李斌 | Hits:

[VHDL-FPGA-Verilog] risc_cpu

Description: 8位risc cpu的编写，使用quartus软件对其进行写入，里面内置乘法器、除法器等模块-8-bit risc cpu the preparation, use the Quartus software to write, which built-in multiplier, divider modules
Platform: | Size: 814080 | Author: 瑞翔 | Hits:

[VHDL-FPGA-Verilog] RISC_Core

Description: 这是用VerilogHDL描述的一个8位精简指令集处理器，包含完整代码，各种文档，以及测试环境。-This is described in VerilogHDL with an 8-bit RISC processor, including the integrity of the code, a variety of documents, as well as the test environment.
Platform: | Size: 316416 | Author: wdy2004 | Hits:

[VHDL-FPGA-Verilog] OR1200_verilog

Description: or1200开源risc cpu的verilog描述实现，cpu源代码分析与芯片设计一书的源码-or1200 open source Verilog description of the risc cpu realize, cpu source code analysis and chip design source book
Platform: | Size: 204800 | Author: yu | Hits:

[VHDL-FPGA-Verilog] RISC

Description: 对ALU中的数据进行操作（实现ADD，SUB,AND,NOT等功能）(Operation of data in ALU (ADD, SUB, AND, NOT and other functions).)
Platform: | Size: 3002368 | Author: 讳忌色 | Hits:
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